As memory devices become more complex and achieve higher densities, it becomes increasingly important to provide comprehensive testing of such devices. It is well known that in very large scale integration (VLSI) integrated circuit designs, memory circuits have a much higher defect density than other logic. Because of the relatively higher defect density rate, memory circuits are commonly subjected to more and more comprehensive testing than other logic in VLSI designs.
One known testing method is to incorporate a built-in memory test controller onto the VLSI chip. Such built-in memory test controllers utilize corresponding memory test algorithms to test memory circuits. While such devices have utility, as designs become larger and more complex, comprehensive testing often requires a number of different tests be run on memory circuits. As a result, built-in memory test controllers can become cumbersome as different types of tests are combined into the built-in controller.
In view of the ever increasing demands for memory testing in ever increasing complexities in circuit chip design, what is needed is a way to perform memory testing that is efficient, flexible and has low complexity.